Postgraduate Course: HPC Architectures (PGPH11080)

Course Outline
School	School of Physics and Astronomy	College	College of Science and Engineering
Credit level (Normal year taken)	SCQF Level 11 (Postgraduate)	Availability	Not available to visiting students
SCQF Credits	10	ECTS Credits	5
Summary	After taking this course students should have a good understanding (from the practioner's perspective) of the way HPC systems are designed and how this affects both the way they are programmed and the performance of applications. The course will cover the following topics: - Basic components of HPC systems: processors, memory, interconnect, storage. - Classification of architectures: SIMD/MIMD, shared vs distributed memory, clusters - System software: OSs, processes, threads, scheduling, batch systems. - Brief history of HPC systems, including Moore &Šs Law. - CPU design: functional units, instructions sets, pipelining, branch predicition, ILP (superscalar, VLIW, SIMD instructions), multithreading. - Caches: operation and design features - Memory: operation and design features, including cache coherency and consistency - Multicore CPUs, including cache and memory hierarchy - GPGPUs: operation and design features - Interconnects: operation and design features - Current HPC architectures Lectures will be followed by tutored practical sessions illustrating the key concepts.
Course description	After taking this course students should have a good understanding (from the practioner's perspective) of the way HPC systems are designed and how this affects both the way they are programmed and the performance of applications. The course will cover the following topics: - Basic components of HPC systems: processors, memory, interconnect, storage. - Classification of architectures: SIMD/MIMD, shared vs distributed memory, clusters - System software: OSs, processes, threads, scheduling, batch systems. - Brief history of HPC systems, including Moore &Šs Law. - CPU design: functional units, instructions sets, pipelining, branch predicition, ILP (superscalar, VLIW, SIMD instructions), multithreading. - Caches: operation and design features - Memory: operation and design features, including cache coherency and consistency - Multicore CPUs, including cache and memory hierarchy - GPGPUs: operation and design features - Interconnects: operation and design features - Current HPC architectures Lectures will be followed by tutored practical sessions illustrating the key concepts.

Entry Requirements (not applicable to Visiting Students)
Pre-requisites		Co-requisites
Prohibited Combinations		Other requirements	None

Course Delivery Information

Academic year 2017/18, Not available to visiting students (SS1)		Quota: None
Course Start	Semester 1
Timetable	Timetable
Learning and Teaching activities (Further Info)	Total Hours: 100 ( Lecture Hours 22, Seminar/Tutorial Hours 11, Summative Assessment Hours 2, Programme Level Learning and Teaching Hours 2, Directed Learning and Independent Learning Hours 63 )
Additional Information (Learning and Teaching)	Please contact the School for further information
Assessment (Further Info)	Written Exam 100 %, Coursework 0 %, Practical Exam 0 %
Additional Information (Assessment)	100% examination consisting of a two hour exam
Feedback	Not entered
Exam Information
Exam Diet	Paper Name		Hours & Minutes
Main Exam Diet S1 (December)			2:00

Learning Outcomes
On completion of this course students should be able to: - Understand the key components of HPC architectures - Understand the basic principles of operation of these components - Appreciate the main design choices and trade-offs in HPC architecture. - Understand how the components are put together to form complete systems - Understand how HPC system software is used to manage the hardware.