Undergraduate Course: Sigma Delta Data Converters 5 (ELEE11082)
Course Outline
School  School of Engineering 
College  College of Science and Engineering 
Credit level (Normal year taken)  SCQF Level 11 (Year 5 Undergraduate) 
Availability  Available to all students 
SCQF Credits  20 
ECTS Credits  10 
Summary  This course will equip the student with an understanding of sigmadelta data converters at a theoretical and practical level. The coursework makes a link between the digital signal processing concepts of sigma delta conversion and implementation in integrated circuit hardware.
The course will briefly review the basics of discretetime signals and systems, before looking at block diagrams and circuit implementations of modulator structures. Saturation, stability and limit cycle behaviour of modulator loops will be described and related to circuit structure. Nonideal behaviour of modulators such as noise, matching, finite gain and settling will be related to circuit level implementations.
The course will be illustrated throughout with MATLAB, Simulink and Cadence Verilog A examples linking to laboratory sessions and a design exercise issued at the start of semester. 
Course description 
Lecture 1:
Reminder of the basics of discretetime signals and systems.
Topics include: sampling, aliasing,interpolation, reconstruction, quantization modelled as noise, and the effects of sampling jitter. General block diagram of oversampled system (ADC and DAC, decimation and interpolation). Frequency domain representation of signals and noise. Fourier series, Fourier transforms and computerbased computational techniques, including the Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), windowing and coherent
sampling principles. Power spectral density (PSD). Averaging
to reduce quantisation noise.
The principles of deltasigma modulation.
Principle of oversampling to reduce the effects of quantization noise, followed by noiseshaping to enhance performance. Block diagram of 1st order modulator. Timedomain model using a firstorder lowpass system then followed by a frequencydomain description. Ztransfer function of NTF and
STF. Inband and filtered noise. Power of noise and signal,
SNR formula. Quantiser gain. Simulink examples.
Lecture 2:
First order modulator continued. Time domain simulation. Limit cycles, idle tones and dither. Dead zone. Simulink examples.
Lecture 3:
Second order modulators.
Secondorder modulator block diagrams. Ztransfer function of NTF, STF. MASH implementation. Single loop implementation. Comparison of 1st and 2nd order. Saturation. Dynamic range scaling equalisation at internal nodes. Limit cycles. Formula of
SNR with modulator order and oversampling. BoserWoolley, SilvaSteensgaard. Error feedback. Simulink examples.
Lecture 4:
Higher order modulators.
Higherorder block diagram. Implementation of higher order modulator as MASH or single loop. Instability. General higher order modulator. Placement of zeros in NTF. Feedback/feedforward to improve THD. NTF comparison. CIFF, CIFB, CRFF, CRFB structures. Matlab SD toolbox for design. Simulink examples.
Lecture 5:
Multibit feedback. Multibit quantisers. Effects on SQNR and stability. Simulink examples.
Lecture 6:
DAC matching effects in multibit DAC. Mismatch effects on modulator linearity. Randomised selection of elements. Dynamic element matching (DEM). Data weighted averaging (DWA). Tones. Tree DEM. Multibit feedback in ADC. Simulink examples.
Lecture 7:
Multistage modulators. 1+1+1, 2+1 MASH, SMASH. Stability. Error term generation. Simulink examples.
Lecture 8:
Circuit Implementation of Modulators.
Non overlapping clock generation.
Switched capacitor implementation of delaying and nondelaying integrators. Latched comparators. 2level DAC implementation. First and second order switched capacitor modulator. Cadence examples.
Lecture 9:
Fully differential switchedcapacitor modulators. Multibit quantiser and DAC implementation.
Switch resistance and transmission gate sizing. Amplifier and switch settling. Synamic range scaling. Cadence examples.
Lecture 10:
Noise sources. 1/f and thermal noise. kT/C noise in switched capacitor modulators. Capacitor sizing for noise. Total modulator noise. Cadence examples.
Lecture 11:
Guest lecture.

Information for Visiting Students
Prerequisites  None 
High Demand Course? 
Yes 
Course Delivery Information

Academic year 2017/18, Available to all students (SV1)

Quota: None 
Course Start 
Semester 2 
Timetable 
Timetable 
Learning and Teaching activities (Further Info) 
Total Hours:
200
(
Lecture Hours 10,
Seminar/Tutorial Hours 5,
Supervised Practical/Workshop/Studio Hours 30,
Formative Assessment Hours 1,
Summative Assessment Hours 12,
Programme Level Learning and Teaching Hours 4,
Directed Learning and Independent Learning Hours
138 )

Assessment (Further Info) 
Written Exam
50 %,
Coursework
50 %,
Practical Exam
0 %

Additional Information (Assessment) 
Coursework (50%) Exam (50%) 
Feedback 
Not entered 
Exam Information 
Exam Diet 
Paper Name 
Hours & Minutes 

Main Exam Diet S2 (April/May)   2:00  
Learning Outcomes
On completion of this course, the student will be able to:
 On completion of the course students will be able to:  understand the operating principles of sigma delta converters
 choose the order, structure and coefficients of sigma delta modulators at a block level 
 employ SIMULINK and MATLAB to simulate and design the modulator coefficients
 use Cadence to study nonideal effects in modulators
 propose circuit implementations of modulators and understand the range of applications of sigmadelta converters.

Reading List
Understanding SigmaDelta Data Converters, Schreier and
Temes, IEEE Press, ISBN 9780471465850 
Additional Information
Graduate Attributes and Skills 
Not entered 
Keywords  Sigmadelta,deltasigma,analogue to digital,digital to analogue,integrated circuits 
Contacts
Course organiser  Dr Robert Henderson
Tel: (0131 6)50 5645
Email: 
Course secretary  Miss Megan Inch
Tel: (0131 6)51 7079
Email: 

