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Home : College of Science and Engineering : School of Engineering and Electronics (Schedule M) : Electronics

Analogue IC Design (P02521)

? Credit Points : 10  ? SCQF Level : 11  ? Acronym : EEL-P-PGANA

This module is a general introduction to analogue integrated circuit design. It will cover the following areas:
• use of IDS equations in circuit calculations;
• use of large signal models to calculate and design transistor biasing;
• use of small signal models to calculate gain-bandwidth, transfer functions;
• the operation & use of analogue circuit building blocks;
- current sources/sinks
- simple amplifiers
- differential stages
- output stages
- basic op-amp design
- gain and phase margin, stability, compensation
- more advanced op-amp concepts
- digital to analogue, and analogue to digital, converters
• use of SPICE to simulate MOS circuits;
• types of analysis available in SPICE, starting with level 1 MOSFET models and moving to BSIM3v3 models;
• use of SPICE to investigate the effects on performance caused by component variation, process variation, temperature changes, etc.
• parasitic components and their importance for circuit modelling;
• sources of noise and distortion in MOS analogue circuits;

? Keywords : analogue integrated circuit design

Entry Requirements

? Pre-requisites : BEng or MEng Electronics and Electrical Engineering degree, or similar

Subject Areas

Delivery Information

? Normal year taken : Postgraduate

? Delivery Period : Not being delivered

? Contact Teaching Time : 3 hour(s) per week for 11 weeks

All of the following classes

Type Day Start End Area
Lecture Monday 09:00 09:50 KB

Summary of Intended Learning Outcomes

Students will be familiar with the details of MOS transistors that are relevant to analogue IC design. They will be familiar with basic analogue circuits. They will be aware how fabrication techniques and processes affect transistor behaviour. They will be able to simulate small analogue circuits and be able to relate the results back to the process and the circuit topology.

Assessment Information

100% exam

Exam times

Diet Diet Month Paper Code Paper Name Length
1ST May 1 - 1 hour(s) 30 minutes

Contact and Further Information

The Course Secretary should be the first point of contact for all enquiries.

Course Secretary

Mrs Kim Orsi
Tel : (0131 6)50 5687
Email : Kim.Orsi@ed.ac.uk

Course Organiser

Dr Martin Reekie
Tel : (0131 6)50 5563
Email : H.M.Reekie@ed.ac.uk

School Website : http://www.see.ed.ac.uk/

College Website : http://www.scieng.ed.ac.uk/

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