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DEGREE REGULATIONS & PROGRAMMES OF STUDY 2006/2007
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Home : College of Science and Engineering : School of Engineering and Electronics (Schedule M) : Electronics

Electrical and Mechanical Engineering 3 (U00774)

? Credit Points : 20  ? SCQF Level : 9  ? Acronym : EEL-3-ELEME

Digital Circuits. Aims: To build on the material presented in the second year and enhance students understanding and design skills of combinational and sequential digital circuit design techniques. To introduce the concepts and techniques for asynchronous sequential design.

Satway: Satway is an exercise in analogue circuit design to realise the circuitry to display a television signal as a picture on a standard oscilloscope.

Entry Requirements

? Pre-requisites : Electronics 2 Electonic Circuits and Devices 2

? Prohibited combinations : Mobile Communications and Multimedia Engineering 3 Digital Electronics 3 Communication Engineering 3

Subject Areas

Delivery Information

? Normal year taken : 3rd year

? Delivery Period : Full Year (Blocks 1-4)

? Contact Teaching Time : 3 hour(s) per week for 22 weeks

Summary of Intended Learning Outcomes

Digital Circuits: Describe the significance of logic swing, propagation delay, power supply requirements, power dissipation, fan in, fan out and be able to compare all the main logic families. Use Karnaugh maps. Implement combinational logic functions using multiplexors or decoders. Convert minimised combinational functions into a form suitable for multi-level implementation, including the use of all NAND or all NOR solutions. Minimise a combinational logic function using the Quine-McCluskey technique and find all minimum solutions using Petrick's method. Design and analyse small synchronous digital circuits which incorporate D, T or JK Flip Flops. Implement small synchronous circuit designs using discrete gates and flip-flops and programmable logic devices. Design and implement a small asynchronous circuit using gates or SR flip-flops.
Satway : At the conclusion of the exercise students should:
- be able to design voltage amplifier, ramp generator and sync. pulse separator circuits.
- be able to implement a multistage amplifier design which withstands the effects of inter-stage loading between successive stages.
- be able to implement effective decoupling in a design.
- be able to integrate a number of separate stages to implement a complete working system to a written specification.
- be able to document a design that they have carried out.
- be able to layout and implement a printed circuit board design.

Assessment Information

1,5 hours Examination(50%) + Laboratory work(50%)

Exam times

Diet Diet Month Paper Code Paper Name Length
1ST December 1 1 1 hour(s) 30 minutes

Contact and Further Information

The Course Secretary should be the first point of contact for all enquiries.

Course Secretary

Mrs Sian Gowans
Tel : (0131 6)50 5687
Email : Sian.Gowans@ed.ac.uk

Course Organiser

Dr Brian Flynn
Tel : (0131 6)50 5590
Email : Brian.Flynn@ed.ac.uk

School Website : http://www.see.ed.ac.uk/

College Website : http://www.scieng.ed.ac.uk/

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